Integrated semiconductor memories can be subdivided into volatile and nonvolatile semiconductor categories. In volatile semiconductor memories, the charges stored in the memory cells always have to be refreshed again within a short time since the stored charges are otherwise lost through leakage currents. In nonvolatile semiconductor memories by contrast, stored information items are retained for a long time, typically several years. One type of volatile semiconductor memory is DRAM (dynamic random access memory), the memory cells of which each has a selection transistor and a storage capacitor. The selection transistor is driven by a word line and a bit line. The storage capacitor becomes accessible if the selection transistor is opened by means of applying suitable bias voltages to the bit line and to the word line. In this case, a stored information item is written in or is read out from the storage capacitor. In addition, after the refresh time has elapsed again, the memory contents of the volatile memory cell are always read out again, amplified and written back into the storage capacitor.
The storage capacitors in a DRAM may be formed for instance as trench capacitors or as stacked capacitors. In the case of the trench capacitor, a deep trench is etched into the semiconductor substrate; the trench wall of the deep trench being first covered with a capacitor dielectric and the trench interior of the deep trench later being filled with a conductive material. The latter forms the inner capacitor electrode. The outer capacitor electrode comprises a doped substrate region in the vicinity of the trench. Electrical contact is made with the outer capacitor electrode with the aid of a buried doped layer (buried layer).
An upper region of the capacitor trench is filled with insulating material in order to prevent leakage currents between selection transistors that are to be arranged at the substrate surface and the trench capacitor. In order to make electrical contact with the inner capacitor electrode, a region of the capacitor dielectric is removed at the upper end of the inner capacitor electrode and conductive material is deposited over it, which material directly touches both the inner capacitor electrode and the trench wall. The deposited conductive material is a doped material whose dopants can outdiffuse into the surrounding substrate material during a thermal treatment carried out in a targeted manner. As a result, a diffusion region is produced which, after carrying out the thermal treatment, reaches as far as a source/drain region of the associated selection transistor and overlaps it. The electrical connection between the selection transistor and the inner capacitor electrode is thereby produced.
The region formed by the outdiffused dopants is usually referred to as a buried strap. Present-day semiconductor memories have memory cells in which the buried strap is arranged only on that side of the edge of the trench capacitor, which faces the selection transistor. The size and conductivity of the buried strap can be controlled by means of the dopant concentration of the inner capacitor electrode (or of the doped material that is deposited on it and reaches as far as the trench wall) and also by means of the duration and the temperature of the thermal treatment.
The selection transistor is usually a MOSFET (metal oxide semiconductor field effect transistor), which has two source/drain regions between which an inversion channel region can be formed. Arranged above the inversion channel region is first the gate oxide, and above that, the gate layer stack, including the gate electrode, which forms an interconnect section of the word line. One of the source/drain regions of the selection transistor is connected to the bit line. The other source/drain region of the selection transistor is connected to the inner capacitor electrode of the trench capacitor by the buried strap.
Integrated semiconductor memories are produced by fabricating a multiplicity of the memory circuits on a semiconductor wafer, and subsequently, singulating the semiconductor wafer into memory chips. In this case, the semiconductor wafer is sawn, or severed in some other way, along interspaces formed between respectively adjacent memory circuits, that is to say along lines of a sawing frame (scribe line). The circuits that have already been formed previously on the semiconductor chips are electrically contact-connected and packaged after the singulation of the wafer.
During the production of the integrated semiconductor circuits on the semiconductor wafer, additional semiconductor structures, in particular test structures, which can supply additional information about the quality of the actual memory circuits during an electrical measurement, can be formed in partial regions of the sawing frame. It is possible, for example, to simulate regions of a memory cell array in a test structure that is to be arranged on the sawing frame and to connect the test structure to external connections in such a way that electrical parameters such as, for instance, nonreactive resistances, leakage currents or others can be determined by means of electrical measurements. Such measurements are carried out by a procedure in which, in a manner similar to that during the electrical functional test of the memory circuits, test needles of a test head are placed onto the wafer surface and make contact with the electrical structures formed. Some test needles may be arranged in such a way that, upon emplacement of the test head, they make contact with a test structure arranged in a sawing frame. Thus, it is possible to carry out electrical measurements, which cannot be carried out in the integrated semiconductor circuit itself.
One electrical measurement quantity of interest in the case of a volatile semiconductor memory is the nonreactive resistance of the buried strap between the selection transistor and the trench capacitor. It is not readily measurable in a completed memory cell array since, although information items may be written to the trench capacitor or read out of the trench capacitor via a bit line, the selection transistor and the buried strap measurement currents cannot be conducted through the buried strap without simultaneously flowing via the channel region of the selection transistor. Therefore, it is never possible to measure the nonreactive resistance of the buried strap in isolation, but rather only the sum of the resistances of the buried strap, of the selection transistor, and of the bit line can be measured. Moreover, a measurement of the nonreactive resistance is made more difficult by the fact that the buried strap is electrically accessible only from one side, whereas the other side of the buried strap is connected to the inner capacitor electrode, which is surrounded by insulating material on all sides.
It is also the case in measurements of other electrical parameters at test structures, where the test structures are modeled on the memory cell arrays, that provision necessarily has to be made of the selection transistors in the test structure via which the measurement currents flow. As a result, measurements of the conductivity of other structure elements, for example of the capacitor electrodes, are also inhibited and affected by the nonreactive resistance of the selection transistor. That is, the measurements of other structure elements cannot be made directly, but are made through the conductive paths of the selection transistors and are, therefore, affected by the nonreactive resistance of the selection transistors.